UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 642

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) Operation procedure
Caution
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 14-39 Procedure for Resuming Master Reception).
After setting the SAUmEN bit of peripheral enable register 0/1 (PER0/PER1) to 1, be sure to set
serial clock select register m (SPSm) after 4 or more f
Setting the PER0/PER1 register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Setting the SPSm register
Setting the SOm register
Stopping communication
Starting communication
Setting the STm register
Starting setting to stop
Starting initial setting
Figure 14-37. Initial Setting Procedure for Master Reception
Figure 14-38. Procedure for Stopping Master Reception
Setting port
Set the initial output level of the serial
clock (CKOmn).
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
and set the SEmn bit to 1 (to enable
operation).
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
MCK
)).
CLK
CHAPTER 14 SERIAL ARRAY UNIT
clocks have elapsed.
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