UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 434

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.5 Channel Output (TOmn pin) Control
8.5.1 TOmn pin output circuit configuration
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Interrupt signal of the master channel
Interrupt signal of the slave channel
The following describes the TOmn pin output circuit.
(Remark is listed on the next page.)
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is
<2>
<3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTMmp (slave
<4> While timer output is disabeled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal)
<5> The TOm register can always be read, and the TOmn pin output level can be checked.
ignored and only INTTMmp (slave channel timer interrupt) is transmitted to timer output register m (TOm).
INTTMmp (slave channel timer interrupt) are transmitted to the TOm register.
At this time, the TOLm register becomes valid and the signals are controlled as follows:
When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp (reset signal)
takes priority, and INTTMmn (set signal) is masked.
channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal)
becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set timer operation is stopeed (TOEmn = 0) and to
write a value to the TOm register.
becomes valid. When timer output is disabeled (TOEmn = 0), neither INTTMmn (master channel timer
interrupt) nor INTTMmp (slave channel timer interrupt) is transmitted to the TOm register.
When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and
When TOLmn = 0:
When TOLmn = 1:
(INTTMmn)
(INTTMmp)
Figure 8-30. Output Circuit Configuration
Forward operation (INTTMmn → set, INTTMmp → reset)
Reverse operation (INTTMmn → reset, INTTMmp → set)
<1>
<2>
TOMmn
TOLmn
TOEmn
<3>
TOmn write signal
<4>
TOmn register
Set
Reset/toggle
<5>
CHAPTER 8 TIMER ARRAY UNIT
Internal bus
TOmn pin
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