UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 460

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.7.4 Operation as input pulse interval measurement
up from 0000H in synchronization with the count clock.
timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter
does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
capture trigger.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured.
The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Timer/counter register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
When TEmn = 1, a software operation (TSmn = 1) can be used as a capture trigger, instead of using the TImn pin input.
Operation clock
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
TImn pin
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Figure 8-53. Block Diagram of Operation as Input Pulse Interval Measurement
TSmn
CKm1
CKm0
detection
Edge
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
register mn (TCRmn)
register mn (TDRmn)
Timer counter
Timer data
CHAPTER 8 TIMER ARRAY UNIT
controller
Interrupt
Interrupt signal
(INTTMmn)
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