UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 755

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note 1
SE
21
0
1
78K0R/Kx3-L
Notes 1. Serial channel enable register 2 (SE2) is a read-only status register which is set using serial channel statrt
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark X: Don’t care
212
MD
Table 14-18. Relationship between register settings and pins (Channel 1 of unit 2: CSI41, UART4 reception)
0
0
0
0
2. When channel 1 of unit 2 is set to UART4 reception, this pin becomes an RxD4 function pin. In this case, set
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART4 transmission and reception in a pair, set channel 0 of unit 2 to UART4 transmission (refer to
6. Serial mode register 20 (SMR20) of channel 0 of unit 2 must also be set during UART4 reception. For details,
211
MD
0
1
0
1
channel 0 of unit 2 to operation stop mode or UART4 transmission (refer to Table 14-17).
When channel 0 of unit 2 is set to CSI40, this pin cannot be used as an RxD4 function pin. In this case, set
channel 1 of unit 2 to operation stop mode or CSI41.
m (SOm).
Table 14-17).
refer to 14.6.2 (1) Register setting.
register 2 (SS2) and serial channel stop register 2 (ST2).
SOE
21
0
0
1
1
0
1
1
0
SO21 CKO
Note 4
Note 4
Note 4
Note 4
0/1
0/1
0/1
0/1
1
1
1
1
Note 4
Note 4
Note 4
0/1
0/1
0/1
21
1
1
1
1
1
TXE
21
0
0
1
1
0
1
1
0
RXE
21
0
1
0
1
1
0
1
1
(
μ
PD78F1027, 78F1028, 78F1029, 78F1030 only)
Note 3
Note 3
PM
53
×
1
1
1
0
0
0
×
Note 3
Note 3
P53 PM54 P54 PM
1
1
1
×
×
×
×
×
Note 3
Note 3
Note 3
Note 3
×
1
×
1
1
×
1
×
Note 3
Note 3
Note 3
Note 3
×
×
×
×
×
×
×
×
Note 3
Note 3
Note 3
Note 3
55
×
×
0
0
×
0
0
×
Note 3
Note 3
Note 3
Note 3
P55 PM
×
×
1
1
×
1
1
×
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 2
51
×
×
×
×
×
×
×
1
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
P51
Note 2
×
×
×
×
×
×
×
×
CHAPTER 14 SERIAL ARRAY UNIT
transmission
transmission
transmission
transmission
Operation
Operation
/reception
/reception
reception
reception
reception
UART4
Notes 5, 6
Master
Master
Master
CSI41
CSI41
CSI41
CSI41
CSI41
CSI41
mode
mode
Slave
Slave
Slave
stop
(output)
(output)
(output)
SCK41/
SCK41
SCK41
SCK41
SCK41
SCK41
SCK41
(input)
(input)
(input)
TI00/
TI00/
TI00/
P53
P53
P53
TO07/
TO07/
TO07/
TO07/
TO07/
TI07/
TI07/
SI41/
TI07/
TI07/
TI07/
SI41
SI41
SI41
SI41
P54
P54
P54
P54
P54
Pin Function
PCLBUZ1/
PCLBUZ1/
PCLBUZ1/
PCLBUZ1/
PCLBUZ1/
INTP7/
INTP7/
INTP7/
INTP7/
INTP7/
SO41/
SO41
SO41
SO41
SO41
P55
P55
P55
P55
P55
INTP2/
INTP2/
INTP2/
INTP2/
INTP2/
INTP2/
INTP2/
INTP2/
RxD4/
RxD4
SI40/
SI40/
SI40/
SI40/
SI40/
SI40/
SI40/
SI40/
Note 2
P51
P51
P51
P51
P51
P51
P51
P51
755