UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 928

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remark The special function register (SFR) mounted depend on the product. See 4.2.4 Special function registers
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Real-time counter
Clock output/buzzer
output controller
Watchdog timer
A/D converter
Serial array unit (SAU)
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
The reset value of WDTE is determined by the option byte setting.
(SFRs) and 4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
Table 21-2. Hardware Statuses After Reset Acknowledgment (2/4)
Sub-count register (RSUBC)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Week count register (WEEK)
Day count register (DAY)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register ALARMWW)
Control register 0 (RTCC0)
Control register 1 (RTCC1)
Control register 2 (RTCC2)
Clock output select registers 0, 1 (CKS0, CKS1)
Enable register (WDTE)
10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
Mode register (ADM)
Analog input channel specification register (ADS)
A/D port configuration register (ADPC)
Serial data registers 00 to 03, 10 to 13, 20, 21 (SDR00 to SDR03, SDR10
to SDR13, SDR20, SDR21)
Serial status registers 00 to 03, 10 to 13, 20, 21 (SSR00 to SSR03, SSR10
to SSR13, SSR20, SSR21)
Serial flag clear trigger registers 00 to 03, 10 to 13, 20, 21 (SIR00 to SIR03,
SIR10 to SIR13, SIR20, SIR21)
Serial mode registers 00 to 03, 10 to 13, 20, 21 (SMR00 to SMR03,
SMR10 to SMR13, SMR20, SMR21)
Serial communication operation setting registers 00 to 03, 10 to 13, 20, 21
(SCR00 to SCR03, SCR10 to SCR13, SCR20, SCR21)
Serial channel enable status registers 0, 1, 2 (SE0, SE1, SE2)
Serial channel start registers 0, 1, 2 (SS0, SS1, SS2)
Serial channel stop registers 0, 1, 2 (ST0, ST1, ST2)
Serial clock select registers 0, 1, 2 (SPS0, SPS1, SPS2)
Serial output registers 0, 1, 2 (SO0, SO1, SO2)
Serial output enable registers 0, 1, 2 (SOE0, SOE1, SOE2)
Serial output level registers 0, 1, 2 (SOL0, SOL1, SOL2)
Input switch control register (ISC)
Hardware
CHAPTER 21 RESET FUNCTION
0000H
00H
00H
12H
00H
01H
01H
00H
00H
00H
12H
00H
00H
00H
00H
00H
1AH/9AH
0000H
00H
00H
00H
10H
0000H
0000H
0000H
0020H
0087H
0000H
0000H
0000H
0000H
0F0FH
0000H
0000H
00H
Acknowledgment
Status After Reset
Note 2
Note 1
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