UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1051

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Notes 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp↓”
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
Remarks 1.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
SCKp cycle time
SCKp high-/low-level width
SIp setup time
(to SCKp↑)
SIp hold time
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(T
A
2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp hold time becomes “from SCKp↓”
3. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from
4. C is the load capacitance of the SOp output lines.
= −40 to +85°C, 1.8 V ≤ V
Parameter
2.
when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
by using port input mode register g (PIMg) and port output mode register g (POMg).
Note 1
when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
SCKp↑” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.
Note 3
Note 2
p: CSI number (p = 00, 01, 10), g: PIM and POM number (g = 3, 7)
f
(Operation clock to be set by the CKS0n bit of the SMR0n register. n: Channel number (n = 0 to 2))
MCK
: Serial array unit operation clock frequency
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
t
t
t
t
t
t
KCY2
KH2
KL2
SIK2
KSI2
KSO2
Symbol
,
DD
= EV
4.0 V ≤ V
1.8 V ≤ V
V
C = 30 pF
DD
≤ 5.5 V, V
DD
DD
Note 4
≤ 5.5 V
< 4.0
Conditions
SS
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
= EV
16 MHz < f
f
MCK
≤ 16 MHz
SS
DD
DD
DD
= AV
≤ 5.5 V
< 4.0 V
< 2.7 V
MCK
SS
= 0 V)
1/f
t
6/f
8/f
6/f
KCY2
MIN.
MCK
80
MCK
MCK
MCK
+50
/2
TYP.
2/f
2/f
2/f
MAX.
MCK
MCK
MCK
+125
+45
+57
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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