UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 695

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
(Essential)
(Essential)
(Essential)
Changing setting of the SDRmn register
Changing setting of the SOEm register
Changing setting of the SOEm register
Changing setting of the SPSm register
Changing setting of the SOm register
Writing to the SSm register
Changing setting of the SMRmn register
Changing setting of the SCRmn register
Changing setting of the SOLm register
Starting setting for resumption
Starting communication
Figure 14-78. Procedure for Resuming UART Transmission
Port manipulation
Port manipulation
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1 and set
the SEmn bit to 1 (to enable operation).
Re-set the register to change the
operation clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (f
Re-set the register to change serial
mode register mn (SMRmn) setting.
Re-set the register to change the serial
communication operation setting register
mn (SCRmn) setting.
Re-set the register to change serial
output level register m (SOLm) setting.
Set the initial output level of the serial
data (SOmn).
Set the SOEmn bit to 1 and enable
output.
Disable data output of the target channel
by setting a port register and a port mode
register.
Clear the SOEmn bit to 0 and stop
Sets transmit data to the TXDq register
(bits 7 to 0 of the SDRmn register) and
start communication.
MCK
)).
CHAPTER 14 SERIAL ARRAY UNIT
695