UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 603

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn
Symbol
Cautions 1. Be sure to clear bit 8 to “0”.
The lower 8 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 8 bits, and during transmission, the data to be transmitted
to the shift register is set to the lower 8 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8 bits of the SDRmn register. When the SDRmn register is read
during operation, 0 is always read.
Reset signal generation clears the SDRmn register to 0000H.
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation
clock (f
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of the SDRmn register is used as the transfer clock.
(Remarks are listed on the next page.)
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13),
FFF4CH, FFF4DH (SDR20), FFF4EH, FFF4FH (SDR21)
MCK
15
0
0
0
0
1
1
•
•
•
).
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these bits
to 0000001B or greater.
are written to, the higher seven bits are cleared to 0.)
14
0
0
0
0
1
1
•
•
•
Figure 14-9. Format of Serial Data Register mn (SDRmn) (1/2)
13
0
0
0
0
1
1
•
•
•
SDRmn[15:9]
FFF11H (SDR00)
12
0
0
0
0
1
1
•
•
•
11
0
0
0
0
1
1
•
•
•
10
0
0
1
1
1
1
•
•
•
9
0
1
0
1
0
1
•
•
•
8
0
Transfer clock setting by dividing the operating clock (f
After reset: 0000H
7
6
CHAPTER 14 SERIAL ARRAY UNIT
5
R/W
FFF10H (SDR00)
f
f
MCK
MCK
f
f
f
f
MCK
MCK
MCK
MCK
4
•
•
•
/254
/256
/2
/4
/6
/8
2
C is used. Set SDRmn[15:9]
3
Bits 7 to 0 function as a
2
1
MCK
)
0
603