UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 526

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UPD78F1000GB-GAF-AX

Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1000GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Address: F0241H (C0CTL), F0242H (C1CTL) After reset: 00H R/W
Symbol
CnCTL
78K0R/Kx3-L CHAPTER 10 COMPARATORS/PROGRAMMABLE GAIN AMPLIFIERS (78K0R/KC3-L, KD3-L, KE3-L only)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Comparator n control register (CnCTL)
(Notes, Cautions, and Remarks are listed on the next page.)
This register is used to control the operation of comparator n, enable or disable comparator output, reverse the
output, and set the noise elimination width.
The CnCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
CnDFS2
CnINV
CnEN
CnEN
CnOE
<7>
0
1
0
0
0
0
1
0
1
0
1
Other than the above
Stops operation
Enables operation
Enables input to the external pins on the positive and negative sides of comparator n
Disables output (output signal = fixed to low level)
Enables output
Forward
Reverse
CnDFS1
6
0
0
0
1
1
0
Figure 10-5. Format of Comparator n Control Register (CnCTL)
Note 3
CnDFS0
5
0
0
1
0
1
0
250 ns
500 ns
Noise filter unused
1
2
Setting prohibited
Enabling or disabling of comparator output
μ
μ
s
s
CnOE
4
Comparator operation control
Output reversal setting
Noise elimination width setting (f
CnINV
3
CnDFS2
2
CLK
CnDFS1
= 20 MHz)
1
Notes 1, 2
CnDFS0
0
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