UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 784

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5.7 Canceling wait
to 1.
value may be output to SDA0 line because the timing for changing the SDA0 line conflicts with the timing for writing the
IICA register.
so that the wait state can be canceled.
IICCTL0 register, so that the wait state can be canceled.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The I
• Writing data to the IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of the IICCTL0 register (generating start condition)
• Setting bit 0 (SPT) of the IICCTL0 register (generating stop condition)
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to the IICA register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of the IICCTL0 register
To generate a restart condition after canceling a wait state, set bit 1 (STT) of the IICCTL0 register to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of the IICCTL0 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICA register after canceling a wait state by setting the WREL bit to 1, an incorrect
In addition to the above, communication is stopped if the IICE bit is cleared to 0 when communication has been aborted,
If the I
Caution If a processing to cancel a wait state is executed when WUP = 1, the wait state will not be canceled.
Note Master only
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of the
2
C cancels the wait state and communication is resumed.
CHAPTER 15 SERIAL INTERFACE IICA
Note
Note
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