UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 197

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
5.2.3 Port 2
Remark √: Mounted
mode register 2 (PM2).
register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit.
the output mode by using the PM2 register.
in the input mode by using the PM2 register. Use these pins starting from the upper bit.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
This port can also be used for A/D converter analog input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in
To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the ADPC register and
All P20/ANI0 to P27/ANI7 are set in the digital input mode when the reset signal is generated.
Figure 5-5 shows a block diagram of port 2.
Caution Make the AV
Digital I/O selection
Analog input selection
ADPC Register
(
μ PD78F100y: y = 0 to 3)
40-pin
78K0R/KC3-L
REF
Table 5-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins
pin the same potential as the V
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
√
√
√
√
√
√
√
√
Input mode
Output mode
Input mode
Output mode
44-pin
PM2 Register
(
μ PD78F100y: y = 1 to 3)
78K0R/KC3-L (48-pin)
Selects ANI.
Does not select ANI.
Selects ANI.
Does not select ANI.
√
√
√
√
√
√
√
√
ADS Register
DD
pin when port 2 is used as a digital port.
−
−
(
μ PD78F100y: y = 4 to 6)
78K0R/KD3-L
√
√
√
√
√
√
√
√
Digital input
Digital output
Analog input (to be converted)
Analog input (not to be converted)
Setting prohibited
P20/ANI0 to P27/ANI7 Pins
(
μ PD78F100y: y = 7 to 9)
78K0R/KE3-L
√
√
√
√
√
√
√
√
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