UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 346

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(2) System clock control register (CKC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
This register is used to select a CPU/peripheral hardware clock and a division ratio.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Address: FFFA4H
Symbol
CKC
Notes 1. Bits 7 and 5 are read-only.
(Remarks and Cautions are listed on the next page.)
CLS
CLS
MCM0
MCS
1
CSS
<7>
Note 5
2. CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 7 is fixed
3. Setting is prohibited if the 1 MHz Internal high-speed oscillation clock frequency (f
4. Setting is prohibited if the high-speed system clock (f
5. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
0
1
0
1
0
1
0
Note 2
Note 2
After reset: 09H
to 0.
selected as the main system clock (f
(f
MAIN
Figure 7-5. Format of System Clock Control Register (CKC)
Main system clock (f
Subsystem clock divided by 2 (f
Internal high-speed oscillation clock (f
(f
High-speed system clock (f
Selects the internal high-speed oscillation clock (f
oscillation clock (f
Selects the high-speed system clock (f
) and if f
IH20
MDIV2
CSS
Other than above
<6>
)
0
0
0
0
1
1
×
MX
< 4 MHz.
R/W
MDIV1
MCS
<5>
IH20
Note 1
0
0
1
1
0
0
×
MAIN
) as the main system clock (f
Status of CPU/peripheral hardware clock (f
)
Main system clock (f
MX
MDIV0
Status of Main system clock (f
)
MCM0
<4>
SUB
0
1
0
1
0
1
×
/2)
MAIN
IH
MX
) or 20 MHz internal high-speed oscillation clock
).
f
f
f
f
f
f
f
Setting prohibited
) as the main system clock (f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
/2
/2 (This is the default setting if MCM0 = 0.)
/2
/2
/2
/2
3
MAIN
1
2
3 Note 3
4 Note 3
5 Notes 3, 4
) operation control
MAIN
IH
) or 20 MHz internal high-speed
Selection of CPU/peripheral
)
CHAPTER 7 CLOCK GENERATOR
MX
hardware clock (f
MDIV2
) is selected as the main system clock
MAIN
2
)
CLK
)
MAIN
MDIV1
1
)
CLK
)
MDIV0
0
IH1
) is
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