UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 759

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.2 Configuration of Serial Interface IICA
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Serial interface IICA includes the following hardware.
(1) IICA shift register (IICA)
(2) Slave address register (SVA)
The IICA register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the
serial clock. The IICA register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to the IICA register.
Cancel the wait state and start data transfer by writing data to the IICA register during the wait period.
The IICA register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Cautions 1. Do not write data to the IICA register during data transfer.
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
The SVA register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD = 1 (while the start condition is detected).
Reset signal generation clears the SVA register to 00H.
Address: FFF50H
2. Write or read the IICA register only during the wait period. Accessing the IICA register in a
3. When communication is reserved, write data to the IICA register after the interrupt triggered
Symbol
IICA
communication state other than during the wait period is prohibited. When the device serves
as the master, however, the IICA register can be written only once after the communication
trigger bit (STT) is set to 1.
by a stop condition is detected.
Registers
Control registers
Item
7
Table 15-1. Configuration of Serial Interface IICA
Figure 15-3. Format of IICA Shift Register (IICA)
After reset: 00H
6
IICA shift register (IICA)
Slave address register (SVA)
Peripheral enable register 0 (PER0)
IICA control register 0 (IICCTL0)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port mode register 6 (PM6)
Port register 6 (P6)
5
R/W
4
Configuration
3
CHAPTER 15 SERIAL INTERFACE IICA
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