UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 854

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol
DMCn
(1) DMA mode control register n (DMCn)
The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a
transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts
DMA.
Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited during operation (when DSTn = 1).
The DMCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark
DMA transfer is performed once by writing 1 to the STGn bit when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DWAITn
DMA transfer that has been held pending can be started by clearing the value of the DWAITn bit to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of the DWAITn bit is set to 1.
STGn
2. When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA transfer
DRSn
STGn
DSn
<7>
0
1
0
1
0
1
0
1
n: DMA channel number (n = 0, 1)
pending for both channels (by setting the DWAIT0 and DWAIT1 bits to 1).
Note 1
Note 2
Figure 17-4. Format of DMA Mode Control Register n (DMCn) (1/2)
No trigger operation
DMA transfer is started when DMA operation is enabled (DENn = 1).
SFR to internal RAM
Internal RAM to SFR
8 bits
16 bits
Executes DMA transfer upon DMA start request (not held pending).
Holds DMA start request pending if any.
DRSn
<6>
After reset: 00H
DSn
<5>
Specification of transfer data size for DMA transfer
DWAITn
Selection of DMA transfer direction
DMA transfer start software trigger
<4>
R/W
Pending of DMA transfer
IFCn3
3
CHAPTER 17 DMA CONTROLLER
IFCn2
2
IFCn1
1
IFCn0
0
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