UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1158

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
2nd edition
Previous
version
(U19291E)
3rd edition
Edition
Change of Table 15-2 Response Time of DMA Transfer
Change of Table 16-1 Interrupt Source List (2/2)
Addition of (C) External maskable interrupt (INTKR) to Figure 16-1. Basic
Configuration of Interrupt Function (2/2)
Change of Caution 2 in 17.3 (1) Key return mode register (KRM)
Addition of Note to Figure 18-3 HALT Mode Release by Interrupt Request
Generation
Change of Note 4 and Caution 1 in Figure 21-2. Format of Low-Voltage Detection
Register (LVIM)
Change of description in 21.4.1 (1) When detecting level of supply voltage (V
Change of description in 21.4.1 (2) When detecting level of input voltage from
external input pin (EXLVI)
Change of description in 21.4.2 (1) When detecting level of supply voltage (V
Change of description in 21.4.2 (2) When detecting level of input voltage from
external input pin (EXLVI)
Change of Figure 21-12. Delay from the time LVI reset source is generated until
the time LVI reset has been generated or released
Addition of Caution 5 to 24.8 Flash Memory Programming by Self-Programming
Change of description in 24.8.2 Flash shield window function
Addition of chapter
Change of On-chip internal high-speed oscillation clocks in 1.1 Features
Change of 1.3 Ordering Information
Addition of 64-pin plastic FBGA (4 × 4) to 1.4.3 78K0R/KE3-L
Change of 1.7 Outline of Functions
Addition of Note to Figures 3-1 to 3-4 Memory Map
Addition of description to 3.1.1 (1) Vector table area
Change of Table 3-5. SFR List (3/4)
Addition of Caution 3 to Figure 4-39. Format of A/D Port Configuration Register
(ADPC)
Change of Figure 5-3. Format of System Clock Control Register (CKC)
Addition of Note and Cautions 3, 6 to Figure 5-4. Format of Clock Operation
Status Control Register (CSC)
Change of Caution 3 in Figure 5-6. Format of Oscillation Stabilization Time
Select Register (OSTS)
Addition of Caution 4 to Figure 5-7. Format of 20 MHz Internal High-Speed
Oscillation Control Register (DSCCTL)
Addition of description to 5.3 (7) Peripheral enable registers 0, 1, 2 (PER0, PER1,
PER2)
Change of Cautions 2 and 3 in Figure 5-9. Format of Operation Speed Mode
Control Register (OSMC)
Change of Caution 7 in Figure 5-9. Format of Operation Speed Mode Control
Register (OSMC)
Change of 5.4.3 Internal high-speed oscillator
Description
APPENDIX B REVISION HISTORY
DD
DD
)
)
CHAPTER 15 DMA
CONTROLLER
CHAPTER 16
INTERRUPT
FUNCTIONS
CHAPTER 18 STANDBY
FUNCTION
CHAPTER 21 LOW-
VOLTAGE DETECTOR
CHAPTER 24 FLASH
MEMORY
APPENDIX B
REVISION HISTORY
CHAPTER 1 OUTLINE
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 17 KEY
INTERRUPT FUNCTION
Chapter
(3/7)
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