HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 111

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Instruction Code
MSB
0010
0010
0010
0011 Rn
0011 Rn
0011 Rn
0011 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rn
0100 Rm Fx
0100 Rm 00MD
0100 Rm 01MD
0100 Rm 10MD
0100 Rm 11MD
0100 Rn
Rm
Rm
Rm
Rm
Fx
Fx
Fx
00MD
01MD
10MD
11MD
Fx
Fx
Fx
LSB
00MD
01MD
10MD
11MD
0000
0001
0010
0011
0011
0011
0011
0100
0101
0110
0111
0111
0111
0111
1000
Fx: 0000
MD: 00
Rn
Rn
Rn
CMP/EQ Rm, Rn
DIV1 Rm, Rn
SUB Rm, Rn
ADD Rm, Rn
SHLL Rn
SHLR Rn
STS.L MACH, @–
Rn
STC.L SR, @–Rn
STC.L SPC, @–Rn
STC.L
R0_BANK, @–Rn
STC.L
R4_BANK, @–Rn
ROTL Rn
ROTR Rn
LDS.L
@Rm+, MACH
LDC.L @Rm+, SR LDC.L @Rm+,
LDC.L @Rm+,
SPC
LDC.L
@Rm+, R0_BANK
LDC.L
@Rm+, R4_BANK
SHLL2 Rn
Fx: 0001
MD: 01
Rm
Rm
Rm
DMULU.L Rm,Rn
DMULS.L Rm,Rn
DT
CMP/PZ Rn
STS.L MACL, @–
Rn
STC.L GBR, @–Rn STC.L VBR, @–
STC.L
R1_BANK, @–Rn
STC.L
R5_BANK, @–Rn
CMP/PL Rn
LDS.L @Rm+,
MACL
GBR
LDC.L
@Rm+, R1_BANK
LDC.L
@Rm+, R5_BANK
SHLL8 Rn
Rn
Rev. 1.00 Dec. 27, 2005 Page 67 of 932
Fx: 0010
MD: 10
01MD
10MD
11MD
CMP/HS Rm, Rn
CMP/HI Rm, Rn
SUBC Rm, Rn
ADDC Rm, Rn
SHAL Rn
SHAR Rn
STS.L PR, @–Rn
Rn
STC.L
R2_BANK, @–Rn
STC.L
R6_BANK, @–Rn
ROTCL Rn
ROTCR Rn
LDS.L @Rm+, PR
LDC.L @Rm+,
VBR
LDC.L
@Rm+, R2_BANK
LDC.L
@Rm+, R6_BANK
SHLL16 Rn
Fx: 0011 to 1111
MD: 11
MOV.B
Rn
TST
CMP/STRRm, Rn
CMP/GE Rm, Rn
CMP/GT Rm, Rn
SUBV
ADDV
STC.L SSR, @–
Rn
STC.L
R3_BANK, @–Rn
STC.L
R7_BANK, @–Rn
LDC.L @Rm+,
SSR
LDC.L
@Rm+, R3_BANK
LDC.L
@Rm+, R7_BANK
REJ09B0269-0100
Section 2 CPU
Rm, Rn
Rm, Rn
Rm, @–
Rm, Rn