HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 268
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Cache
6.3.3
Prefetch Hit: The LRU is updated to indicate that the hit way is the most recently hit way. The
other contents of the cache are not changed. Instructions and data are not transferred from the
cache to the CPU.
Prefetch Miss: Instructions and data are not transferred from the cache to the CPU. The way that
is to be replaced is shown in table 6.2. The other operations are the same as those for a read miss.
6.3.4
Write Hit: In a write access in write-back mode, the data is written to the cache and no external
memory write cycle is issued. The U bit of the entry that has been written to is set to 1, and the
LRU is updated to indicate that the hit way is the most recently hit way. In write-through mode,
the data is written to the cache and an external memory write cycle is issued. The U bit of the
entry that has been written to is not updated, and the LRU is updated to indicate that the hit way is
the most recently hit way.
Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the
entry is updated. The way to be replaced is shown in table 6.3. When the U bit of the entry which
is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been
transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set
to 1. The LRU is updated to indicate that the replaced way is the most recently updated way. After
the cache has completed its update cycle, the write-back buffer writes the entry back to the
memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write
miss; the write is only to the external memory.
6.3.5
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 6.3 shows the configuration of the write-back buffer.
Rev. 1.00 Dec. 27, 2005 Page 224 of 932
REJ09B0269-0100
Prefetch Operation
Write Access
Write-Back Buffer
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