HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 582

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Dec. 27, 2005 Page 538 of 932
REJ09B0269-0100
Bit
15 to 8
7
6
5
Bit Name

C/A
CHR
PE
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Communication Mode
Selects asynchronous mode or clock synchronous
mode as the SCIF operating mode.
0: Asynchronous mode
1: Clock synchronous mode
Character Length
Selects 7 or 8 bits as the asynchronous mode data
length. In clock synchronous mode, a fixed data
length of 8 bits is used regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Parity Enable
In asynchronous mode, selects whether or not parity
bit addition is performed in transmission, and parity
bit checking in reception. In clock synchronous mode,
parity bit addition and checking is not performed,
regardless of the PE bit setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*
Note: * When 7-bit data is selected, the MSB (bit 7)
Note: * When the PE bit is set to 1, the parity (even
of the transmit FIFO data register (SCFTDR)
is not transmitted.
or odd) specified by the O/E bit is added to
transmit data before transmission. In
reception, the parity bit is checked for the
parity (even or odd) specified by the O/E bit.