HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 74

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Table 2.1
2.2.2
The LSI uses 29 bits of the 32-bit logical address to access external memory. In this case, 0.5-
Gbyte of external memory space can be accessed. The external memory space is managed in area
units. Different types of memory can be connected to each area, as shown in figure 2.2. For
details, please refer to section 12, Bus State Controller (BSC).
In addition, area 1 in the external memory space is used as an on-chip I/O space where most of
this LSI’s on-chip I/Os are mapped. *
Normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are
used for external memory addresses.*
H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3
area of the logical address space are mapped into address H’00000100 of area 0 in the external
memory space. The P4 area in the logical address space is not mapped into the external memory
address. If an address in the P4 area is accessed, an external memory cannot be accessed.
Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the
Rev. 1.00 Dec. 27, 2005 Page 30 of 932
REJ09B0269-0100
Address Range Name
H'00000000 to
H'7FFFFFFF
H'80000000 to
H'9FFFFFFF
H'A0000000 to
H'BFFFFFFF
H'C0000000 to
H'DFFFFFFF
H'E0000000 to
H'FFFFFFFF
2. If the address translation unit is enabled, arbitrary mapping in page units can be
External Memory Space
address from the P2 area which is not cached in the logical address space.
specified. For details, refer to section 5, Memory Management Unit (MMU).
Logical Address Space
P0/U0
P1
P2
P3
P4
Mode
Privileged/user mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
1
2
For example, address H'00000100 in the P0 area, address
Description
2-Gbyte physical space, cacheable, address
translatable
In user mode, only this address space can be
accessed.
0.5-Gbyte physical space, cacheable
0.5-Gbyte physical space, non-cacheable
0.5-Gbyte physical space, cacheable, address
translatable
0.5-Gbyte control space, non-cacheable