HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 533

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bus Mode and Channel Priority: Even if channel 1 is performing burst-mode transfer in priority
fixed mode (CH0 > CH1), channel 0 starts transfer immediately when a request is made for
transfer on channel 0 with higher priority.
If channel 0 is also in burst mode at this time, channel 1 resumes transfer after transfer on channel
0 with higher priority is completed.
If channel 0 is in cycle-steal mode, channel 0 with higher priority transfers one transfer unit then
allows channel 1 to perform transfers without releasing bus mastership. Next, transfers are
performed alternately by channel 0, channel 1, channel 0, channel 1, and so on. This means that a
bus state is set for the CPU cycle after completion of the cycle-steal mode transfer is replaced with
the burst-mode transfer. (This operation is hereinafter referred to as burst-mode priority
execution.) Figure 13.11 shows an example.
If multiple channels are conflicting in burst mode, the channel with the highest priority is selected
for execution.
If multiple channels perform DMA transfers, bus mastership is not released to the bus master until
all conflicting burst transfers are completed.
In round-robin mode, the priority changes according to the specification shown in figure 13.11.
However, no mixture of channels in cycle-steal mode and channels in burst mode is allowed.
13.4.5
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 12, Bus State Controller (BSC).
Number of Bus Cycle States and DREQ Pin Sampling Timing
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Figure 13.11 Bus State when Multiple Channels are Operating
CPU
CPU
DMA
CH1
DMAC CH1
Burst mode
DMA
CH1
DMA
CH0
CH0
DMAC CH0 and CH1
Cycle-steal mode in
DMA
CH1
CH1
Section 13 Direct Memory Access Controller (DMAC)
DMA
CH0
CH0
Rev. 1.00 Dec. 27, 2005 Page 489 of 932
DMA
CH1
DMAC CH1
Burst mode
DMA
CH1
CPU
CPU
REJ09B0269-0100