HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 513

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
13.3.5
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register indicates the DMA transfer status.
DMAOR is initialized to H′0000 at a reset and retains the current value in standby or module
standby mode.
Bit
0
Bit
15 to
10
9
8
*
Bit Name
DE
Bit Name

PR1
PR0
DMA Operation Register (DMAOR)
Only 0 can be written to clear the flag.
Initial
Value
0
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
R/W
R/W
Descriptions
DMA Enable
Enables or disables the DMA transfer. In auto-request
mode, DMA transfer starts by setting the DE bit and DME bit
in DMAOR to 1. In this time, all of the bits TE, NMIF in
DMAOR, and AE in DMAOR must be 0. In an external
request or peripheral module request, DMA transfer starts if
DMA transfer request is generated by the devices or
peripheral modules after setting the bits DE and DME to 1.
In this case, however, all of the bits TE, NMIF, and AE must
be 0 as in the case of auto-request mode. Clearing the DE
bit to 0 can terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Priority Mode
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Reserved (setting prohibited)
11: All channel round-robin mode
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 469 of 932
REJ09B0269-0100