HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 363

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Notes: * The input clock is 1.
Mode
7
1. Use the CKIO frequency within 33.34 MHz ≤ CKIO ≤ 66.67 MHz.
2. The input to divider 1 is the output of PLL circuit 1.
3. Use the internal clock frequency within 33.34 MHz ≤ Iφ ≤ 200.00 MHz.
4. Use the peripheral clock frequency within 8.34 MHz ≤ Pφ ≤ 33.34 MHz.
5. × 1, × 2, or × 3 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, or × 1/3
6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
FRQCR
Value
1103
1104
1204
The internal clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the IFC bit in FRQCR.
Do not set the internal clock frequency lower than the CKIO pin frequency.
The peripheral clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the PFC bit in FRQCR.
Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
can be selected as the division ratio of an internal clock. × 1/2, × 1/3, × 1/4, or
× 1/6 can be selected as the division ratio of a peripheral clock. Set the rate in FRQCR.
multiplication ratio of PLL circuit 1. Use the output frequency under 200.00 MHz.
Maximum frequency: Iφ = 200.00 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz
PLL
Circuit 1
On (x2)
On (x2)
On (x3)
PLL
Circuit 2
Off
Off
Off
Clock
Ratio*
(I:B:P)
2:1:1/2
2:1:1/3
3:1:1/2
Frequency Range of
Input Clock and
Crystal Resonator
33.34 MHz to
66.67 MHz
33.34 MHz to
66.67 MHz
33.34 MHz to
66.67 MHz
Rev. 1.00 Dec. 27, 2005 Page 319 of 932
Section 11 On-Chip Oscillation Circuits
Frequency Range of
CKIO Pin
33.34 MHz to 66.67
MHz
33.34 MHz to 66.67
MHz
33.34 MHz to 66.67
MHz
REJ09B0269-0100