HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 169
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3.5.6
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point operations as shown in table 3.21.
The ALU logical operation is executed between registers. Each source and destination operand is
selected independently from one of the DSP registers. As shown in figure 3.15, this type of
operation uses only the upper word of each operand. The lower word and guard-bit parts are
ignored for the source operand and those of the destination operand are automatically cleared.
These operations are also executed in the DSP stage, as shown in figure 3.10. The DSP stage is the
same stage as the MA stage in which memory access is performed.
Table 3.24 Variation of ALU Logical Operations
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
Mnemonic
PAND
POR
PXOR
ALU Logical Operations
39
31
Source 1
Function
Logical AND
Logical OR
Logical exclusive OR
Figure 3.15 ALU Logical Operation Flow
39
31
Destination
0
ALU
39
Source 1
Sx
Sx
Sx
31
Source 2
0
Rev. 1.00 Dec. 27, 2005 Page 125 of 1044
DSR
Source 2
Sy
Sy
Sy
Ignored
Cleared to 0
0
GT Z
Section 3 DSP Operating Unit
N
V DC
REJ09B0269-0100
Destination
Dz
Dz
Dz
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