HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 600

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and
SCFRDR.
Bits 12 to 8 show the number of transmit data bytes in SCFTDR, and bits 4 to 0 show the number
of receive data bytes in SCFRDR.
SCFDR can be read by the CPU at all times.
SCFDR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state, and retains its contents.
Rev. 1.00 Dec. 27, 2005 Page 556 of 932
REJ09B0269-0100
Bit
2
1
0
Bit Name
TFRST
RFRST
LOOP
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of
Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of
Loopback Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD), and RTS pin and CTS pin,
enabling loopback testing.
0: Loopback test disabled
1: Loopback test enabled
a power-on reset or manual reset.
a power-on reset or manual reset.