HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 173

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Arithmetic Shift: Figure 3.17 shows the arithmetic shift operation flow.
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from –32 to
+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
2. Negative Value Mode: CS[2:0] = 001
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The DC bit indicates the last shifted out data as the operation result.
Shift out
Shift amount data
(source 2)
32 31
base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard-
bit parts when a register not providing the guard-bit parts is specified as the source
operand. When a register not providing the guard-bit parts is specified as a destination
operand, the lower 32 bits of the operation result are input into the destination register.
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Left shift
16 15
Figure 3.17 Arithmetic Shift Operation Flow
32 31
>=0
+32- -32
23 22 16
6
Imm1
0
Sy
<0
0
15
0
39
(MSB copy)
0
Updated
32 31
Rev. 1.00 Dec. 27, 2005 Page 129 of 1044
Ignored
Section 3 DSP Operating Unit
Right shift
DSR
16 15
GT
REJ09B0269-0100
Z
Shift out
N
0
V DC