HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 654

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
17.3.11 Serial Receive Data Register (SIRDR)
SIRDR is used to read receive data of the SIOF. SIRDR stores data in the receive FIFO. SIRDR is
initialized by a power-on reset, software reset, or receive reset.
Rev. 1.00 Dec. 27, 2005 Page 610 of 932
REJ09B0269-0100
Bit
31 to 16
15 to 0
Bit Name
SIRDL15 to
SIRDL0
SIRDR15 to
SIRDR0
Initial
Value
All 0
All 0
R/W
R
R
Description
Left Channel Receive Data
Store data received from the RXD_SIO pin as left channel
data. The position of the left channel data in a receive
frame is specified by the RDLA bit in SIRDAR.
These bits are valid only when the RDLE bit in SIRDAR is
set to 1.
Right Channel Receive Data
Store data received from the RXD_SIO pin as right
channel data. The position of the right channel data in the
reception frame is specified by the RDRA bit in SIRDAR.
These bits are valid only when the RDRE bit in SIRDAR is
set to 1.