HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 679

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.5
Note the following when using the SIOF.
1. Using the transmit function in slave mode
2. Using control data transmission/reception consecutively on control data interface (secondary
3. DMA transfer
4. Access from the CPU
5. Transmit/receive FIFO underflow
6. Transmit/receive reset execution
If transmission is enabled when data has already been written to the transmit FIFO, one or two
of the first data bytes may be lost.
Therefore, data should not be written to the transmit FIFO before enabling transmission.
FS position)
The TCRDY value may become 1 before transmit control data is sent, and if the next control
data is written to the control data register at this point, the control data waiting to be sent will
be overwritten and erased.
At this time, also, the control sequence is disrupted and the SIOF switches around the primary
FS and secondary FS, with the result that transmission/reception of data and control data can
no longer be performed normally.
The control data register should therefore be written to after transmit control data has been
sent.
Example:
Check RCRDY, and write to the control data register when RCRDY is 1.
After transmit control data has been written to, it is essential to read the receive control register
(SIRCR) and clear RCRDY.
Do not use 16-byte DMA transfer. (See section 13.4.4, DMA Transfer Types.)
When performing access from the CPU, do not access the SIOF's transmit/receive FIFO
consecutively, but instead insert an access to somewhere else between SIOF transmit/receive
FIFO accesses.
If the transmit/receive FIFO underflows during a transmit/receive operation, control of the
SIOF's transmit/receive FIFO may fail and data may be lost.
To prevent this, either set a watermark so that an underflow does not occur, or execute a
transmit reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated.
When using the SIOF again after a transmit/receive operation ends, or after erroneous
operation occurs, first execute a transmit reset (TXRST) or receive reset (RXRST).
Usage Notes
Rev. 1.00 Dec. 27, 2005 Page 635 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100