HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 445
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 445 of 980
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Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected
without external multiplexing circuitry according to the setting of bits BSZ[1:0]in CSnBCR,
AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.12 to 12.17 show the relationship between the
settings of bits BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins.
Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is
not guaranteed. A25 to A18 are not multiplexed and the original values of address are always
output at these pins.
When the data bus width is 16 bits (BSZ[1:0] =B’10), A0 of SDRAM specifies a word address.
Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the
A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B’11), the A0 pin of
SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of
the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
This LSI
Figure 12.13 Example of 16-Bit Data-Width SDRAM Connection
DQMLU
DQMLL
RD/WR
CKIO
CKE
RAS
CAS
CSn
A14
D15
D0
A1
Rev. 1.00 Dec. 27, 2005 Page 401 of 932
Section 12 Bus State Controller (BSC)
64-Mbit synchronous SDRAM
(1M x 16 bits x 4 banks)
A13
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
REJ09B0269-0100
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