HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 307

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
9.1
The UBC has the following features:
1. The following break comparison conditions can be set.
• Address
• Data
• Bus cycle
• Read/write
• Operand size
2. A user-designed user-break condition exception processing routine can be run.
UBCS300B_000020020900
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
Compares 40 bits configured of the ASID and addresses 32 bits: the ASID can be selected
either all-bit comparison or all-bit mask. Comparison bits are maskable in 1-bit units; user can
mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc.
One of the four address buses (logic address bus (LAB), internal address bus (IAB),
X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected.
Only on channel B, 32-bit maskable.
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB)
and Y-memory data bus (YDB)) can be selected.
Instruction fetch or data access
Byte, word, and longword
Features
Section 9 User Break Controller
Rev. 1.00 Dec. 27, 2005 Page 263 of 932
Section 9 User Break Controller
REJ09B0269-0100