HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 701

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)
MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast
address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
18.3.20 IPG Register (IPGR)
IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting
and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to
section 18.4.8, Operation by IPG Setting.)
Bit
31 to 0 MAFC31 to
Bit
31 to 5 
4 to 0
Bit Name
MAFC0
Bit Name
IPG4 to
IPG0
Initial
Value
All 0
Initial
Value
All 0
H′13
R/W
R/W
R/W
R
R/W
Description
Multicast Address Frame Count
These bits indicate the count of multicast frames
received.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Inter Packet Gap
Sets the IPG value every 4-bit time.
H′00: 20-bit time
H′01: 24-bit time
H′13: 96-bit time (Default)
H′1F: 144-bit time
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Rev. 1.00 Dec. 27, 2005 Page 657 of 932
Section 18 Ethernet Controller (EtherC)
REJ09B0269-0100