HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 99

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
OP:
Sz:
SRC: Source
DEST: Destination
Destination register
Operation code
Size
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
instruction execution states will be increased in cases such as the following:
a.
b.
When there is a conflict between an instruction fetch and a data access
When the destination register of a load instruction (memory → register) is also used
by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Memory operand
Rev. 1.00 Dec. 27, 2005 Page 55 of 932
Privilege
Indicates a
privileged
instruction.
Execution
States
Value
when no
wait states
are
inserted *
REJ09B0269-0100
Section 2 CPU
1
T Bit
Value of T
bit after
instruction
is
executed
Explanatio
n of
Symbols
—: No
change