HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 332

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 User Break Controller
• Register specifications
• Register specifications
Rev. 1.00 Dec. 27, 2005 Page 288 of 932
REJ09B0269-0100
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
The ASID check is not included.
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with ASID = H’80 and address H'00037226 is executed, a user break
occurs before an instruction with ASID = H’70 and address H'0003722E is executed.
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
The ASID check is not included.
<Channel B>
Address:
Data:
The ASID check is not included.
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
H'00037226, Address mask: H'00000000, ASID = H'80
H'0003722E, Address mask: H'00000000, ASID = H'70
H'00000000, Data mask: H'00000000
H'00027128, Address mask: H'00000000
H'00031415, Address mask: H'00000000
H'00000000, Data mask: H'00000000
included in the condition)