HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 168

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
Table 3.23 Variation of ALU Integer Operations
Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base
In ALU integer arithmetic operations, the lower word of the source operand is ignored and the
lower word of the destination operand is automatically cleared. The guard-bit parts are effective in
integer arithmetic operations if they are supported. Others are basically the same operation as
ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation
provides two kinds of instructions only, so that the second operand is actually either +1 or –1.
When a word data is loaded into one of the DSP unit’s registers, it is input as an upper word data.
When a register providing guard bits is specified as an operand, the guard bits are also activated.
These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in
figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. This is the same as fixed-point
operations but the lower word of each source and destination operand is not used in order to
generate them. See section 3.5.4, ALU Fixed-Point Operations, for details.
In case of a conditional operation, they are not updated even though the specified condition is true
and the operation is executed. In case of an unconditional operation, they are always updated in
accordance with the operation result. See section 3.5.4, ALU Fixed-Point Operations, for details.
• Overflow Protection
Rev. 1.00 Dec. 27, 2005 Page 124 of 1044
REJ09B0269-0100
Mnemonic
PINC
PDEC
The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section
3.5.11, Overflow Protection, for details.
precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts
when a register not providing the guard-bit parts is specified as the source operand. When
a register not providing the guard-bit parts is specified as a destination operand, the upper
word excluding the guard bits of the operation result are input into the destination register.
Function
Increment by 1
Decrement by 1
Source 1
Sx
+1
Sx
–1
Source 2
+1
Sy
–1
Sy
Destination
Dz
Dz
Dz
Dz