HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 795

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.2.17 Transmit Descriptor Fetch Address Register (TDFAR)
TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the transmission descriptor. Which transmission descriptor information is used
for processing by the E-DMAC can be recognized by monitoring addresses displayed in this
register. The address from which the E-DMAC is actually fetching a descriptor may be different
from the value read from this register.
19.2.18 Overflow Alert FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC. The threshold
can be specified by the size of the receive FIFO data (RFD2 to RFD0) and the number of receive
frames (RFF2 to RFF0).
If the same receive FIFO size as set by the FIFO size register (FDR) is set when flow control is
turned on according to the RFD setting condition, flow control is turned on with (FIFO data size −
64) bytes. For instance, when RFD in FDR = 7 and RFD in FCFTR = 7, flow control is turned on
when (2048 − 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this
register should be equal to or less than those in FDR.
Flow control is turned on when any of the setting conditions of the RFF2 to RFF0 bits or the
RFD2 to RFD0 bits is satisfied. Flow control is turned off when none of the conditions is satisfied
(release).
Bit
31 to 0
Bit Name
TDFA31 to
TDFA0
Initial
Value
All 0
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R
Description
These bits can only be read. Writing is prohibited.
Transmission-Descriptor Fetch Address
Rev. 1.00 Dec. 27, 2005 Page 751 of 932
REJ09B0269-0100