HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 503

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The direct memory access controller (DMAC) can be used in place of the CPU to perform high-
speed transfers between external devices that have DACK (transfer request acknowledge signal),
external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral
modules.
13.1
• Six channels (Two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, Word (two bytes), Longword (four bytes), and 16 bytes
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests:
• Bus mode: Cycle steal mode or burst mode can be selected.
• Channel priority levels: The channel priority levels are selectable between fixed mode and
• Interrupt request: An interrupt request can be generated to the CPU at the end of the specified
• External request detection: There are following four types of DREQ input detection.
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
(longword × 4)
An external request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
SCIF0, SCIF1, SIOF0, SIOF1
round-robin mode.
counts of data transfer.
Low-level detection
High-level detection
Rising-edge detection
Falling-edge detection
can be set independently.
Section 13 Direct Memory Access Controller (DMAC)
Features
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 459 of 932
REJ09B0269-0100