HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 565

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
6
5
4
3
2
1
0
Bit Name
CIE
AIE
AF
Initial Value
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit
enables interrupts.
0: A carry interrupt is not generated when the CF
1: A carry interrupt is generated when the CF flag
Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
0: An alarm interrupt is not generated when the
1: An alarm interrupt is generated when the AF
Reserved
These bits are always read as 0. The write value
should always be 0.
Alarm Flag
The AF flag is set to 1 when the alarm time set in
an alarm register (only registers with the ENB bit
of the corresponding alarm registers and YAEN
bit in RCR3 set to 1) matches the clock and
calendar time. This flag is cleared to 0 when 0 is
written, but holds the previous value when 1 is to
be written.
0: Clock/calendar and alarm register have not
1: Clock/calendar and alarm register have
flag is set to 1
is set to 1
AF flag is set to 1
flag is set to 1
matched.
Clearing condition: When 0 is written to AF
matched.
Setting condition: Clock/calendar and alarm
register have matched (only registers with the
ENB bit and YAEN bit in RCR3 set to 1)
Rev. 1.00 Dec. 27, 2005 Page 521 of 932
Section 15 Realtime Clock (RTC)
REJ09B0269-0100

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