HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 346

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Power-Down Modes
10.3
10.3.1
Transition to Sleep Mode: Executing the SLEEP instruction when the STBY bit in STBCR is 0
causes a transition from the program execution state to sleep mode. Although the CPU halts
immediately after executing the SLEEP instruction, the contents of its internal registers remain
unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues
to be output to the CKIO pin. In sleep mode, a high signal and low signal are output from the
STATUS1 and STATUS0 pins, respectively.
Canceling Sleep Mode: Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, or on-chip
peripheral module) or reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1.
If necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
• Canceling with an Interrupt
• Canceling with a Reset
Rev. 1.00 Dec. 27, 2005 Page 302 of 932
REJ09B0269-0100
Bit
1
0
When an NMI, IRQ, IRL, or on-chip peripheral module interrupt occurs, sleep mode is
canceled and interrupt exception handling is executed. A code indicating the interrupt source is
set in INTEVT and INTEVT2.
Sleep mode is canceled by a power-on reset or a manual reset.
Operation
Sleep Mode
Bit Name
MSTP31
MSTP30
Initial Value R/W
0
0
R/W
R/W
Description
Module Stop Bit 31
When the MSTP31 bit is set to 1, the supply of the
clock to the SCIF1 is halted.
0: The SCIF1 runs
1: Clock supply to the SCIF1 halted
Module Stop Bit 30
When the MSTP30 bit is set to 1, the supply of the
clock to the SCIF0 is halted.
0: The SCIF0 runs
1: Clock supply to the SCIF0 halted