HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 198

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
Notes: 1. For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual.
Rev. 1.00 Dec. 27, 2005 Page 154 of 1044
REJ09B0269-0100
Instruction Code
MSB
1000 01MD
1000 10MD
1000 11MD
1001 Rn
1010 disp
1011 disp
1100 00MD
1100 01MD
1100 10MD
1100 11MD
1101 Rn
1110 Rn
1111 00**
1111 01**
1111 10**
1111 11**
2. Instructions in the hatched areas are DSP extended instructions. These instructions can
be executed only when the DSP bit of the SR register is set to 1.
Rm
imm/disp
imm/disp
disp
imm/disp
disp
imm
imm
disp
imm
********
********
********
********
LSB
disp
Fx: 0000
MD: 00
MOV.B
@(disp:4, Rm), R0
CMP/EQ #imm:8, R0
LDRS @(disp:8,PC)
MOV.W
BRA
BSR
MOV.B
R0, @(disp: 8, GBR)
MOV.B
@(disp: 8, GBR), R0
TST #imm: 8, R0
TST.B
#imm: 8, @(R0, GBR)
MOV.L
MOV
MOVX.W, MOVY.W Double data transfer instruction
MOVS.W, MOVS.L Single data transfer instruction
MOVX.W, MOVY.W Double data transfer instruction, with DSP parallel operation instruction
(32-bit instruction )
disp : 12
disp: 12
@(disp: 8, PC), Rn
#imm:8, Rn
@(disp : 8, PC), Rn
Fx: 0001
MD: 01
MOV.W
@(disp: 4, Rm), R0
BT
BT/S disp: 8
MOV.W
R0, @(disp: 8, GBR)
MOV.W
@(disp: 8, GBR), R0
AND
AND.B
#imm: 8, @(R0, GBR)
disp: 8
#imm: 8, R0
Fx: 0010
MD: 10
LDRE @(disp:8,PC)
MOV.L
R0, @(disp: 8, GBR)
MOV.L
@(disp: 8, GBR), R0
XOR
XOR.B
#imm: 8, @(R0, GBR)
#imm: 8, R0
Fx: 0011 to 1111
MD: 11
BF
BF/S disp: 8
TRAPA
MOVA
@(disp: 8, PC), R0
OR
OR.B
#imm: 8, @(R0, GBR)
disp: 8
#imm: 8, R0
#imm: 8