HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 235

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.2.2
The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
5.2.3
The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
5.2.4
The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU
settings described in figure 5.3. Any program that modifies MMUCR should reside in the P1 or P2
area.
Bit
31 to 29
28 to 10
9
8
7
6, 5
4
3
2
1
0
Page Table Entry Register Low (PTEL)
Translation Table Base Register (TTB)
MMU Control Register (MMUCR)
Bit Name

PPN

V

PR
SZ
C
D
SH

Initial
Value
All 0

0

0





0
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Physical Page
Page management information
For more details, see section 5.3, TLB Functions
Section 5 Memory Management Unit (MMU)
Rev. 1.00 Dec. 27, 2005 Page 191 of 932
REJ09B0269-0100