HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 41

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 X/Y Memory
Table 7.1
Table 7.2
Section 8 Interrupt Controller (INTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Section 9 User Break Controller
Table 9.1
Table 9.2
Table 9.3
Section 10 Power-Down Modes
Table 10.1
Table 10.2
Table 10.3
Section 11 On-Chip Oscillation Circuits
Table 11.1
Table 11.2
Table 11.3
Section 12 Bus State Controller (BSC)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Table 12.10
Table 12.11
Table 12.12
Table 12.12
X/Y Memory Logical Addresses .......................................................................... 231
MMU and Cache Settings..................................................................................... 234
Pin Configuration.................................................................................................. 237
Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 240
Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 243
Interrupt Level and INTEVT Code....................................................................... 245
Interrupt Sources and IPRA to IPRI ..................................................................... 247
Specifying Break Address Register ...................................................................... 269
Specifying Break Data Register............................................................................ 271
Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 284
States of Power-Down Modes .............................................................................. 296
Pin Configuration.................................................................................................. 298
Register States in Software Standby Mode........................................................... 303
Pin Configuration.................................................................................................. 315
Clock Operating Modes ........................................................................................ 315
Possible Combination of Clock Mode and FRQCR Values.................................. 317
Pin Configuration.................................................................................................. 334
Address Space Map 1 (CMNCR.MAP = 0).......................................................... 338
Address Space Map 2 (CMNCR.MAP = 1).......................................................... 339
Correspondence between External Pins (MD3 and MD4), Memory Type of
CS0, and Memory Bus Width............................................................................... 340
Correspondence between External Pin (MD5) and Endians ................................. 340
32-Bit External Device/Big Endian Access and Data Alignment ......................... 384
16-Bit External Device/Big Endian Access and Data Alignment ......................... 385
8-Bit External Device/Big Endian Access and Data Alignment........................... 386
32-Bit External Device/Little Endian Access and Data Alignment ...................... 387
16-Bit External Device/Little Endian Access and Data Alignment ...................... 388
8-Bit External Device/Little Endian Access and Data Alignment ........................ 389
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-1............................................................................ 402
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-2............................................................................ 404
Rev. 1.00 Dec. 27, 2005 Page xxxix of xlii