HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 669

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Transmission in Slave Mode: Figure 17.11 shows an example of settings and operation for slave
mode transmission.
No.
6
7
8
9
2
4
5
1
3
in SIRDR synchronously with SIOFSYNC
Store receive data from RXD_SIO
Start SCK_SIO clock transmission
SIRDAR, SICDAR, and SIFCTR
Set SIMDR, SISCR, SITDAR,
Clear RXE bit in SICTR to 0
Set SCKE bit in SICTR to 1
Figure 17.10 Example of Reception Operation in Master Mode
Set FSE bit in SICTR to 1
Set RXE bit in SICTR to 1
Read SIRDR
RDREQ=1?
Time Chart
Receive
ended?
Start
End
Yes
Yes
No
No
Set operation start for baud rate
generator
Set the start for frame
synchronous signal
Set to enable reception
Read receive data
Set to disable reception
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
SIOF Settings
Rev. 1.00 Dec. 27, 2005 Page 625 of 932
Section 17 Serial I/O with FIFO (SIOF)
Transmit serial clock
Transmit frame
synchronous signal
Submit reception request
according to the receive
FIFO threshold value
End reception
Reception
SIOF Operation
REJ09B0269-0100