HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 613

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
No
No
No
No
Read receive data in SCFRDR
Clear DR, ER, and BRK flags
in SCFSR and ORER flag
Overrun error handling
Receive error handling
Break handling
in SCLSR to 0
Error handling
ORER = 1?
BRK = 1?
Figure 16.7 Sample Serial Reception Flowchart (2)
DR = 1?
ER = 1?
End
Yes
Yes
Yes
Yes
Section 16 Serial Communication Interface with FIFO (SCIF)
1. Whether a framing error or parity error has
2. When a break signal is received, receive
occurred in the receive data read from
SCFRDR can be ascertained from the FER
and PER bits in SCFSR.
data is not transferred to SCFRDR while
the BRK flag is set. However, note that the
last data in SCFRDR is H'00 and the break
data in which a framing error occurred is
stored.
Rev. 1.00 Dec. 27, 2005 Page 569 of 932
REJ09B0269-0100

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