HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 440

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Bus State Controller (BSC)
12.5.3
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 12.9.
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Rev. 1.00 Dec. 27, 2005 Page 396 of 932
REJ09B0269-0100
Access Wait Control
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)
Read
Write
Note: * The waveform for DACKn is when active low is specified.
A25 to A0
D31 to D0
D31 to D0
DACKn*
WEn (BEn)
RD/WR
CKIO
CSn
RD
BS
T1
Tw
T2