HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 17

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.7
Section 6 Cache .................................................................................................215
6.1
6.2
6.3
6.4
Section 7 X/Y Memory......................................................................................231
7.1
7.2
7.3
Section 8 Interrupt Controller (INTC) ...............................................................235
8.1
8.2
5.6.2
5.6.3
Usage Note......................................................................................................................... 213
Features.............................................................................................................................. 215
6.1.1
Register Descriptions ......................................................................................................... 217
6.2.1
6.2.2
6.2.3
Operation ........................................................................................................................... 222
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Memory-Mapped Cache .................................................................................................... 226
6.4.1
6.4.2
6.4.3
Features.............................................................................................................................. 231
Operation ........................................................................................................................... 232
7.2.1
7.2.2
7.2.3
Usage Notes ....................................................................................................................... 233
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Features.............................................................................................................................. 235
8.1.1
Input/Output Pins ............................................................................................................... 237
Data Array ............................................................................................................ 211
Usage Examples.................................................................................................... 213
Cache Structure..................................................................................................... 215
Cache Control Register 1 (CCR1) ........................................................................ 217
Cache Control Register 2 (CCR2) ........................................................................ 218
Cache Control Register 3 (CCR3) ........................................................................ 221
Searching the Cache.............................................................................................. 222
Read Access.......................................................................................................... 223
Prefetch Operation ................................................................................................ 224
Write Access ......................................................................................................... 224
Write-Back Buffer ................................................................................................ 224
Coherency of Cache and External Memory .......................................................... 225
Address Array ....................................................................................................... 226
Data Array ............................................................................................................ 227
Usage Examples.................................................................................................... 230
Access from CPU.................................................................................................. 232
Access from DSP .................................................................................................. 232
Access from DMAC and E-DMAC ...................................................................... 233
Page Conflict ........................................................................................................ 233
Bus Conflict .......................................................................................................... 233
MMU and Cache Settings..................................................................................... 233
Sleep Mode ........................................................................................................... 234
Address Error........................................................................................................ 234
Block Diagram...................................................................................................... 235
Rev. 1.00 Dec. 27, 2005 Page xv of xlii