HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 265

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 6.5
Table 6.6
6.2.3
The CCR3 register controls the cache size to be used. The cache size must be specified according
to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the
LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the
CCR3 register should be placed in un-cached address space. In addition, note that all cache entries
must be invalidated by setting the CF bit of the CCR1 to 1 before accessing the cache after the
CCR3 is modified.
LRU (Bits 5 to 0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
LRU (Bits 5 to 0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Bit
31 to 24
23 to 16
15 to 0
Cache Control Register 3 (CCR3)
Bit Name
—
CSIZE7 to
CSIZE0
—
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)
Initial
Value
All 0
H’01
All 0
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Size
Specify the cache size as shown below.
0000 0001: 16-kbyte cache
0000 0010: 32-kbyte cache
Settings other than above are prohibited.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Dec. 27, 2005 Page 221 of 932
Way to be Replaced
2
1
0
Way to be Replaced
1
0
REJ09B0269-0100
Section 6 Cache