HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 267

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU i
Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown
in table 6.3. Entries are updated in 16-byte units. When the desired instruction or data that caused
the miss is loaded from external memory to the cache, the instruction or data is transferred to the
CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared
to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U
bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache-
update cycle starts after the entry is transferred to the write-back buffer. After the cache completes
its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte
units.
s
updated to indicate that the hit way is the most recently hit way.
31
Virtual address
Read Access
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Physical address
MMU
Entry selection
13 12
511
CMP0 CMP1 CMP2 CMP3
0
1
V U Tag address
Hit signal 1
Figure 6.2 Cache Search Scheme
4 3 2 1 0
Ways 0 to 3
Longword (LW) selection
LW0
Rev. 1.00 Dec. 27, 2005 Page 223 of 932
LW1
LW2
Ways 0 to 3
LW3
REJ09B0269-0100
Section 6 Cache

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