HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 275

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI has on-chip X-memory and Y-memory which can be used to store instructions or data.
7.1
• Page
• Memory map
Table 7.1
On the other hand, this memory is located in a part of area 1 in the physical address space. When
this memory is accessed from the physical address space, addresses in which the upper three bits
are 0 in addresses shown in table 7.1 are used. In the X-bus and Y-bus address spaces, addresses in
which the upper 16 bits are ignored in addresses of X memory and Y memory shown in table 7.1
are used.
• Ports
Page
Page 0 of X memory
Page 1 of X memory
Page 0 of Y memory
Page 1 of Y memory
There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y
memory is divided into two pages (pages 0 and 1).
The X/Y memory is located in the logical address space, physical address space, and X-bus
and Y-bus address spaces.
In the logical address space, this memory is located in the addresses shown in table 7.1. These
addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP
= 1) according to the CPU operating mode.
Each page has three independent read/write ports and is connected to each bus. The X memory
is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus,
and L bus. The L bus is used when this memory is accessed from the logical address space.
The I bus is used when this memory is accessed from the physical address space. The X bus
and Y bus are used when this memory is accessed from the X-bus and Y-bus address spaces.
Features
X/Y Memory Logical Addresses
Section 7 X/Y Memory
Memory Size (Total Four Pages)
16 kbytes
H′A5007000 to H′A5007FFF
H′A5008000 to H′A5008FFF
H′A5017000 to H′A5017FFF
H′A5018000 to H′A5018FFF
Rev. 1.00 Dec. 27, 2005 Page 231 of 932
Section 7 X/Y Memory
REJ09B0269-0100