HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 172
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 3 DSP Operating Unit
result is aligned to the LSB of the destination, but the fixed-point multiply operation result is
aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0.
Multiply is always unconditional, but does not affect any condition code bits, DC, N, Z, V, and
GT , in DSR.
• Overflow Protection
3.5.8
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation.
The correspondence between each operand and registers, except for immediate operands, is the
same as the ALU fixed-point operations as shown in table 3.21.
Table 3.27 Variation of Shift Operations
Rev. 1.00 Dec. 27, 2005 Page 128 of 1044
REJ09B0269-0100
Mnemonic
PSHA Sx, Sy, Dz
PSHL Sx, Sy, Dz
PSHA #Imm1, Dz
PSHL #Imm2, Dz
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0))
operation is executed as signed fixed-point multiply. The result is H'00 8000 0000 but it
does not mean (+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF
FFFF.
Shift Operations
Function
Arithmetic shift
Logical shift
Arithmetic shift with
immediate.
Logical shift with
immediate.
Source 1
Sx
Sx
Dz
Dz
–32 <= Imm1 <= +32, –16 <= Imm2 <= +16
Source 2
Sy
Sy
Imm1
Imm2
Destination
Dz
Dz
Dz
Dz
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