HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 805

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Ethernet frame is received. In such a case, the received Ethernet frame is transferred sequentially
to buffers, 500 bytes for each buffer, starting with the first descriptor. Only the last 14 bytes are
transferred to the fourth buffer. When a frame longer than RBL of a descriptor is received, the
E-DMAC transfers the remaining data to the receive buffer by using the subsequent descriptors.
As an example of efficient single-frame/multi-buffer operation, information items on different
processing layers in an Ethernet frame can be separated from each other by using different buffers.
For example, the destination address, transmit source address, and type field data in an Ethernet
frame can be stored in buffer 1 (with RBL set to 14 bytes) and the remaining data can be stored in
buffer 2 (with RBL set to 1500 bytes). All receive frames, of course, can be stored in a single
buffer if multiple descriptors are prepared and RBL of each descriptor is set to more than 1514
bytes (maximum Ethernet frame length).
RD0
RD1
RD2
Note: * According to the descriptor length set by the DL0 and DL1 bits in EDMR, the padding size is determined as follows:
For 16 bytes: Padding = 4 bytes
For 32 bytes: Padding = 20 bytes
For 64 bytes: Padding = 52 bytes
Receive descriptor
31 30 29 28 27 26
31
31
R
C
A
T
Figure 19.3 Relationship between Receive Descriptor and Receive Buffer
R
D
E
L
R
P
F
1
R
P
F
0
RBL
R
F
E
Padding (4/20/52 bytes)*
16
RBA
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
RFS26 to RFS0
15
RDL
0
0
0
Rev. 1.00 Dec. 27, 2005 Page 761 of 932
Receive buffer
Valid receive data
REJ09B0269-0100