HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 116

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
instruction fields consist of two fields: field A and field B. In field A, a function for double data
transfer instructions can be descried. In field B, ALU operation instructions and multiply
instructions can be described. The instructions described in fields A and B can be executed in
parallel. A maximum of four instructions (ALU operation, multiply, and two data transfers) can be
executed in parallel. For details, refer to section 3.5, DSP Data Operation Instructions.
Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes.
Rev. 1.00 Dec. 27, 2005 Page 72 of 1044
REJ09B0269-0100
2. In little endian, the upper and lower words must be stored in memory as data to be
Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit
instruction codes must be stored in memory, upper word and lower word, in this order,
in word units.
accessed in word units.
CPU core instruction
Double-data transfer instruction
Single-data transfer instruction
DSP data operation instruction
15
15
15
31
Figure 3.1 DSP Instruction Format
0000
1110
111100
111101
111110
26 25
12 11
10
10
9
9
A Field
A Field
A Field
*
16
0
0
0
15
B Field
0